module IR (
        input [31:0] D,
        input  CLK,
        input  IRWr,
        output reg [5:0] opcode,
        output reg [4:0] rs,
        output reg [4:0] rt,
        output reg [4:0] rd,
        output reg [4:0] shamt,
        output reg [5:0] func,
        output reg [15:0] immediate_16,
        output reg [25:0] immediate_26

    );

    //TODO: state control;
    always @(posedge CLK) begin
        if (IRWr) begin
            opcode<=D[31:26];
            rs<=D[25:21];
            rt<=D[20:16];
            rd<=D[15:11];
            shamt<=D[10:6];
            func<=D[5:0];
            immediate_16<=D[15:0];
            immediate_26<=D[25:0];
        // end
        // else begin
        //     opcode<=opcode;
        //     rs<=rs;
        //     rt<=rt;
        //     rd<=rd;
        //     shamt<=shamt;
        //     func<=func;
        //     immediate_16<=immediate_16;
        //     immediate_26<=immediate_26;
        end
    end
endmodule




